module top_mul_tc_16_16
(	input clk,
	input rst_n,
    input   [15:0]  a,
    input   [15:0]  b,

    output reg [31:0]  product
);

    reg   [15:0]    a_r;
    reg   [15:0]    b_r;
    wire  [31:0]    product_r;
	mul_tc_16_16 inst_mul_tc_16_16 (.a(a_r), .b(b_r), .product(product_r));
always @(posedge clk ) begin
    if (!rst_n) begin
        product <=    32'b0;
        a_r     <=    16'b0;
        b_r     <=    16'b0;
    end
    else begin
        product <=      product_r;
        a_r     <=      a;
        b_r     <=      b;
    end
end     


endmodule
